/* fsl_edma.h */

#ifndef __FSL_EDMA_H__
#define __FSL_EDMA_H__

#include <stdint.h>
#include <stdbool.h>

/*
* Enumeration.
*/

typedef enum
{
    eDMAMUX_TriggerSource_Disabled = 0U,
    eDMAMUX_TriggerSource_UART0_Rx = 2U,
    eDMAMUX_TriggerSource_UART0_Tx = 3U,
    eDMAMUX_TriggerSource_UART1_Rx = 4U,
    eDMAMUX_TriggerSource_UART1_Tx = 5U,
    eDMAMUX_TriggerSource_UART2_Rx = 6U,
    eDMAMUX_TriggerSource_UART2_Tx = 7U,
    eDMAMUX_TriggerSource_UART3_Rx = 8U,
    eDMAMUX_TriggerSource_UART3_Tx = 9U,
    eDMAMUX_TriggerSource_UART4_Rx = 10U,
    eDMAMUX_TriggerSource_UART4_Tx = 11U,
    eDMAMUX_TriggerSource_I2S0_RX  = 12U,
    eDMAMUX_TriggerSource_I2S0_TX  = 13U,
    eDMAMUX_TriggerSource_SPI0_Rx  = 14U,
    eDMAMUX_TriggerSource_SPI0_Tx  = 15U,
    eDMAMUX_TriggerSource_SPI1_RxOrTx  = 16U,
    eDMAMUX_TriggerSource_SPI2_RxOrTx  = 17U,
    eDMAMUX_TriggerSource_I2C0         = 18U,
    eDMAMUX_TriggerSource_I2C1orI2C2   = 19U,
    eDMAMUX_TriggerSource_FTM0_CH0 = 20U,
    eDMAMUX_TriggerSource_FTM0_CH1 = 21U,
    eDMAMUX_TriggerSource_FTM0_CH2 = 22U,
    eDMAMUX_TriggerSource_FTM0_CH3 = 23U,
    eDMAMUX_TriggerSource_FTM0_CH4 = 24U,
    eDMAMUX_TriggerSource_FTM0_CH5 = 25U,
    eDMAMUX_TriggerSource_FTM0_CH6 = 26U,
    eDMAMUX_TriggerSource_FTM0_CH7 = 27U,
    eDMAMUX_TriggerSource_FTM1_CH0 = 28U,
    eDMAMUX_TriggerSource_FTM1_CH1 = 29U,
    eDMAMUX_TriggerSource_FTM2_CH0 = 30U,
    eDMAMUX_TriggerSource_FTM2_CH1 = 31U,
    eDMAMUX_TriggerSource_FTM3_CH0 = 32U,
    eDMAMUX_TriggerSource_FTM3_CH1 = 33U,
    eDMAMUX_TriggerSource_FTM3_CH2 = 34U,
    eDMAMUX_TriggerSource_FTM3_CH3 = 35U,
    eDMAMUX_TriggerSource_FTM3_CH4 = 36U,
    eDMAMUX_TriggerSource_FTM3_CH5 = 37U,
    eDMAMUX_TriggerSource_FTM3_CH6 = 38U,
    eDMAMUX_TriggerSource_FTM3_CH7 = 39U,
    eDMAMUX_TriggerSource_ADC0  = 40U,
    eDMAMUX_TriggerSource_ADC1  = 41U,
    eDMAMUX_TriggerSource_CMP0  = 42U,
    eDMAMUX_TriggerSource_CMP1  = 43U,
    eDMAMUX_TriggerSource_CMP2  = 44U,
    eDMAMUX_TriggerSource_DAC0  = 45U,
    eDMAMUX_TriggerSource_DAC1  = 46U,
    eDMAMUX_TriggerSource_CMT   = 47U,
    eDMAMUX_TriggerSource_PDB   = 48U,
    eDMAMUX_TriggerSource_PORT_PTA = 49U,
    eDMAMUX_TriggerSource_PORT_PTB = 50U,
    eDMAMUX_TriggerSource_PORT_PTC = 51U,
    eDMAMUX_TriggerSource_PORT_PTD = 52U,
    eDMAMUX_TriggerSource_PORT_PTE = 53U,
    eDMAMUX_TriggerSource_IEEE1588_Timer0 = 54U,
    eDMAMUX_TriggerSource_IEEE1588_Timer1 = 55U,
    eDMAMUX_TriggerSource_IEEE1588_Timer2 = 56U,
    eDMAMUX_TriggerSource_IEEE1588_Timer3 = 57U,
    eDMAMUX_TriggerSource_DMAMUX_AlwaysEnable0 = 58U,
    eDMAMUX_TriggerSource_DMAMUX_AlwaysEnable1 = 59U,
    eDMAMUX_TriggerSource_DMAMUX_AlwaysEnable2 = 60U,
    eDMAMUX_TriggerSource_DMAMUX_AlwaysEnable3 = 61U,
    eDMAMUX_TriggerSource_DMAMUX_AlwaysEnable4 = 62U,
    eDMAMUX_TriggerSource_DMAMUX_AlwaysEnable5 = 63U,
    eDMAMUX_TriggerSource_PIT = 64U
} DMAMUX_TriggerSource_T;

typedef enum
{
    eEDMA_BusWidth_1Byte = 0U, /* 8-bit. */
    eEDMA_BusWidth_2Byte = 1U, /* 16-bit. */
    eEDMA_BusWidth_4Byte = 2U  /* 32-bit. */
} EDMA_BusWidth_T;

typedef enum
{
    eEDMA_AddrCycle_Disabled    = 0U,
    eEDMA_AddrCycleModulo_16B   = 1U,
    eEDMA_AddrCycleModulo_32B   = 2U,
    eEDMA_AddrCycleModulo_64B   = 3U,
    eEDMA_AddrCycleModulo_128B  = 4U,
    eEDMA_AddrCycleModulo_256B  = 5U,
    eEDMA_AddrCycleModulo_512B  = 6U,
    eEDMA_AddrCycleModulo_1KB   = 7U,
    eEDMA_AddrCycleModulo_2KB   = 8U,
    eEDMA_AddrCycleModulo_4KB   = 9U,
    eEDMA_AddrCycleModulo_8KB   = 10U,
    eEDMA_AddrCycleModulo_16KB  = 11U,
    eEDMA_AddrCycleModulo_32KB  = 12U,
    eEDMA_AddrCycleModulo_64KB  = 13U,
    eEDMA_AddrCycleModulo_128KB = 14U,
    eEDMA_AddrCycleModulo_256KB = 15U
} EDMA_AddrCycleMode_T;


/*
* Structure.
*/

typedef struct
{
    /* Basic settings. */
    uint32_t SrcAddr;
    uint32_t DestAddr;
    uint32_t MinorLoopByteCount; /* Continuous bytes send by minor loop. */
    /* Bit width of each transfer. */
    EDMA_BusWidth_T SrcBusWidthMode;
    EDMA_BusWidth_T DestBusWidthMode;

    /* Address cycle. */
    EDMA_AddrCycleMode_T SrcAddrCycleMode;
    EDMA_AddrCycleMode_T DestAddrCycleMode;

    /* Minor loop. */
    /* Offset for next transfer's address of source and destination. */
    int32_t SrcAddrIncPerTransfer; /* Increasment for next transfer. */
    int32_t DestAddrIncPerTransfer;
    int32_t SrcAddrMinorLoopDoneOffset; /* Offset when minor loop is done. */
    int32_t DestAddrMinorLoopDoneOffset;

    /* Major loop. */
    /* Count of minor loop in a major loop. */
    uint32_t MinorLoopCount;
    /* Address Offset on totally transfer done. */
    int32_t SrcAddrMajorLoopDoneOffset; 
    int32_t DestAddrMajorLoopDoneOffset;

} EDMA_TransferConfig_T;

/*
* API.
*/

/* DMAMUX. */
void DMAMUX_SetTriggerForDMA(uint32_t chnIdx, DMAMUX_TriggerSource_T trigger);

/* DMA Engine. */
void EDMA_ResetEngine(void);
void EDMA_SetMinorLoopOffsetEnabled(bool enable);

/* DMA TCD (Transfer-control Descriptor). */
void EDMA_ResetChannel(uint32_t chnIdx);
bool EDMA_ConfigTransfer(uint32_t chnIdx, EDMA_TransferConfig_T *configPtr);

bool EDMA_IsMajorLoopDone(uint32_t chnIdx);
void EDMA_ClearMajorLoopDoneFlag(uint32_t chnIdx);
void EDMA_ClearIntFlagOfMajorLoopDone(uint32_t chnIdx);
void EDMA_SetIntEnabledOnMajorLoopDone(uint32_t chnIdx, bool enable);
void EDMA_SetIntEnabledOnHalfMajorLoopDone(uint32_t chnIdx, bool enable);

/* Trigger. */
void EDMA_SwTriggerCmd(uint32_t chnIdx);
void EDMA_SetHwTriggerEnabled(uint32_t chnIdx, bool enable);
void EDMA_SetHwTriggerAutoDisabledOnMajorLoopDone(uint32_t chnIdx, bool enable);

#endif /* __FSL_EDMA_H__ */


